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/// Map standard XCPU defines for intrinsics usage.
/// vc++: There are no native flags for SHA and SSE41.
#if defined(HAVE_XCPU)
// -msha
// vc++: SHANI not independently configurable (requires custom option).
#if defined(__SHA__)
#define HAVE_SHANI
#define HAVE_SHA
#endif
// -mavx512bw
// vc++: Advanced Vector Extensions 512 (X86/X64) (/arch:AVX512)
#if defined(__AVX512BW__)
#define HAVE_AVX512
#define HAVE_512
#endif
// -mavx2
// vc++: Advanced Vector Extensions 2 (X86/X64) (/arch:AVX2)
#if defined(__AVX2__)
#define HAVE_AVX2
#define HAVE_256
#endif
// -msse4.1
// vc++: Use Advanced Vector Extensions (X86/X64) (/arch:AVX).
#if defined(__SSE4_1__)
#define HAVE_SSE4
#define HAVE_128
#endif
#endif
/// Map standard ARM defines for intrinsics usage.
/// SVE maximum width is not detectable (requires custom options).
#if defined(HAVE_ARM)
// -march=armv8-a+crypto
// Requires 64 bit build.
#if defined(__ARM_FEATURE_CRYPTO)
#define HAVE_CRYPTO
#define HAVE_SHA
#endif
// -march=armv8-a+sve
// Requires 64 bit build.
#if defined(__ARM_FEATURE_SVE)
#define HAVE_SVE
#endif
// -march=armv8-a (64 bit)
// -march=armv7-a -mfpu=neon -mfloat-abi=hard (32 bit)
#if defined(__ARM_NEON)
#define HAVE_NEON
#define HAVE_128
#endif
#endif